Equivalent time sampling oscilloscopes use undersampling of periodic high speed data waveforms to produce an eye diagram. An eye diagram is a superposition of the various logic states of a data waveform and is a common way to assess the integrity of the signal. Particularly, an eye diagram is a useful means for readily obtaining information regarding voltage swing and transition time of the incoming data. However, the various forms of jitter are not well characterized with eye diagrams.
Jitter is the general term used to describe the noise or uncertainty in the period of incoming data in a communications system. In an ideal communications system, bits arrive at time increments that are integer multiples of a bit repetition time. However, in a real-world system, data pulses arrive at times that deviate from these integer multiples. This deviation may case errors in the transmission of data, particularly when the data is transmitted at high speeds.
Jitter is composed of intersymbol interference (ISI), duty-cycle distortion (DCD), periodic jitter (PJ) and random jitter (RJ). ISI is caused by data path propagation delay which is a function of past data history and can be caused by transmission line reflections. DCD can be caused by propagation delay differences between low to high and high to low transitions. DCD is manifested as a deviation from a 50% duty cycle. PJ is cyclic jitter that is caused by sinusoidal interference. RJ is the remaining random component of the jitter and is assumed to have a Gaussian distribution. In the relation to the present discussion, ISI, DCD and PJ are referred to as deterministic jitter.
Jitter is a problem of particular importance in digital communication systems and can cause the received signal to be sampled at a non-optimal sampling point. This increases the bit-error ratio at the receiver and thus limits the data rate. In conventional systems, each receiver typically extracts its clock from the incoming data signal. Jitter makes this task significantly more difficult.
Existing sampling oscilloscopes rely on sequential delay generators to delay sampling events relative to a trigger event, causing the trace to build up from left to right across the display. The existing system requires a well characterized sequential time delay generator. Time delay generators are adversely influenced by temperature variations and are inaccurate when long time delays are required. To analyze the deterministic jitter of a data pattern, the location of the rising and falling edges of the waveform must be known. One of the problems with sampling systems utilizing time delay generators is that the time delay to edges far from the trigger can be long, particularly in longer patterns. The long delay causes a significant amount of inaccuracy in the sequential delay generator.
FIG. 1 illustrates a block diagram of such a prior art sampling system 10. The input waveform 11 to be sampled is applied to the input of a sampler 12. The times at which the waveform is sampled is determined by a trigger signal 22 and sequential delay generator 14. The delay generator adds incrementally increasing delay times to the trigger signal 22 and sends sampling strobe signals 24 to the sampler 12. Upon receiving the strobe signals, the sampler 12 produces a value that is representative of the amplitude of the input waveform and sends this value to the CPU 16 for processing. As sample points are gradually collected at increasing times from the trigger signal 22, the waveform is acquired. The system 10 in FIG. 1, as stated above, has disadvantages. For instance, the system requires that the sequential delay generator 14 be well characterized. In addition, the system 10 has unwanted temperature dependencies and other inaccuracies, particularly when long delay times are added to the trigger signal. Therefore the system 10 in FIG. 1 cannot be used to accurately measure deterministic jitter in long patterns.
Another known sampling system uses a counter in conjunction with a fine delay generator. This system uses the data clock instead of a trigger signal to generate the sample events. The counter can be used to count many clock cycles to generate long delays, thereby eliminating the inaccuracies associated with long delays using a sequential time delay generator mentioned above. FIG. 2 illustrates a block diagram of such a prior art sampling system 50. The input waveform 53 to be sampled is applied to the input of a sampler 60. The times at which the waveform is sampled is determined by a synchronous clock 55, prescaler 57, programmable counter 65 and fine delay generator 75. The prescaler 57 divides the synchronous clock 55 down to a frequency that is within the frequency range of the counter 65. The counter 65 and fine delay generator 75 are programmed to progressively vary the time delay of the strobe signals 61 sent to the sampler. Upon receiving a strobe signal, the sampler 60 produces a value that is representative of the amplitude of the input waveform 53 and sends this value to the CPU 70 for processing. As sample points are gradually collected, the waveform is acquired. While the system 50 in FIG. 2 does not have the problem of inaccurate long delays as with the system in FIG. 1, the fine delay generator must still be well characterized. In addition, the sample rate for long patterns becomes exceedingly slow, thereby making deterministic jitter measurements of long patterns unnecessarily time consuming.
There is a need for a versatile sampling system that performs a novel method of measuring high data rate digital waveform signals and producing eye diagrams from the measurements. What is also needed is a versatile sampling system capable of performing jitter analysis of DCD and ISI jitter components when measuring the high-speed digital signals.